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rev. c information furnished by analog devices is believed to be accurate and reliable. however, no responsibility is assumed by analog devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. no license is granted by implication or otherwise under any patent or patent rights of analog devices. a AD7660 * one technology way, p.o. box 9106, norwood, ma 02062-9106, u.s.a. tel: 781/329-4700 www.analog.com fax: 781/326-8703 ? analog devices, inc., 2002 16-bit, 100 ksps cmos adc functional block diagram switched cap dac 16 control logic and calibration circuitry clock AD7660 data[15:0] busy rd cs ser/ par ob/ 2c ognd ovdd dgnd dvdd avdd agnd ref refgnd in ingnd pd reset serial port parallel interface cnvst features throughput: 100 ksps inl: 3 lsb max ( 0.0046% of full-scale) 16 bits resolution with no missing codes s/(n+d): 87 db min @ 10 khz, 90 db typ @ 45 khz thd: C96 db max @ 10 khz analog input voltage range: 0 v to 2.5 v both ac and dc specifications no pipeline delay parallel and serial 5 v/3 v interface spi?/qspi?/mi crowire?/ dsp compatible single 5 v supply operation 21 mw typical power dissipation, 21 w @ 100 sps power-down mode: 7 w max package: 48-lead quad flatpack (lqfp) pin-to-pin compatible with the ad7664 applications data acquisition battery-powered systems pcmcia instrumentation automatic test equipment scanners medical instruments process control general description the AD7660 is a 16-bit, 100 ksps, charge redistribution sar, analog-to-digital converter that operates from a single 5 v power supply. the part contains an internal conversion clock, error cor- rection circuits, and both serial and parallel system interface ports. the AD7660 is hardware factory calibrated and is comprehensively tested to ensure such ac parameters as signal-to-noise ratio (snr) and total harmonic distortion ( thd), in addition to the more traditional dc parameters of gain, offset, and linearity. it is fabricated using analog devices high-performance, 0.6 micron cmos process with correspondingly low cost, and is available in a 48-lead lqfp with operation specified from C40 c to +85 c. product highlights 1. fast throughput the AD7660 is a 100 ksps, charge redistribution, 16-bit sar adc with internal error correction circuitry. 2. superior inl the AD7660 has a maximum integral nonlinearity of 3 lsbs with no missing 16-bit code. 3. single-supply operation the AD7660 operates from a single 5 v supply and only dissipates 21 mw typical. its power dissipation decreases with the throughput to, for instance, only 21 w at a 100 sps throughput. it consumes 7 w maximum when in power-down. 4. serial or parallel interface versatile parallel or 2-wire serial interface arrangement com- patible with both 3 v or 5 v logic. * patent pending spi and qspi are trademarks of motorola, inc. microwire is a trademark of national semiconductor corporation
AD7660?pecifications (?0 c to +85 c, avdd = dvdd = 5 v, ovdd = 2.7 v to 5.25 v, unless otherwise noted.) rev. c C2C parameter conditions min typ max unit resolution 16 bits analog input voltage range v in C v ingnd 0v ref v operating input voltage v in C0.1 +3 v v ingnd C0.1 +0.5 v analog input cmrr f in = 25 khz 70 db leakage current at 25 c 100 ksps throughput 325 na input impedance see analog input section throughput speed complete cycle 10 s throughput rate 0 100 ksps dc accuracy integral linearity error C3 +3 lsb 1 differential linearity error C1 +1.75 lsb no missing codes 16 bits transition noise 2 0.75 lsb full-scale error 3 ref = 2.5 v 0.045 0.08 % of fsr unipolar zero error 3 1 5 lsb power supply sensitivity avdd = 5 v 5% 3 lsb ac accuracy signal-to-noise f in = 10 khz 87 90 db 4 f in = 45 khz 90 db spurious free dynamic range f in = 10 khz 96 db f in = 45 khz 100 db total harmonic distortion f in = 10 khz C96 db f in = 45 khz C100 db signal-to-(noise+distortion) f in = 10 khz 87 db f in = 45 khz 90 db C60 db input 30 db C3 db input bandwidth 820 khz sampling dynamics aperture delay 2ns aperture jitter 5 ps rms transient response full-scale step 8 s reference external reference voltage range 2.3 2.5 avdd C 1.85 v external reference current drain 100 ksps throughput 22 a power supplies specified performance avdd 4.75 5 5.25 v dvdd 4.75 5 5.25 v ovdd 2.7 5.25 v operating current 100 ksps throughput avdd 3.2 ma dvdd 5 1ma ovdd 5 10 a power dissipation 5 100 ksps throughput 21 25 mw 100 sps throughput 21 w in power-down mode 5, 6 7 w digital inputs logic levels v il C0.3 +0.8 v v ih +2.0 ovdd + 0.3 v i il C1 +1 a i ih C1 +1 a digital outputs data format parallel or serial 16-bit pipeline delay conversion results available immediately after completed conversion v ol i sink = 1.6 ma 0.4 v v oh i source = C500 a ovdd C 0.6 v
rev. c C3C AD7660 parameter conditions min typ max unit temperature range specified performance t min to t max C40 +85 c notes 1 lsb means least significant bit. with the 0 v to 2.5 v input range, one lsb is 38.15 v. 2 typical rms noise at worst-case transitions and temperatures. 3 see definition of specifications section. these specifications do not include the error contribution from the external referenc e. 4 all specifications in db are referred to a full-scale input fs. tested with an input signal at 0.5 db below full-scale unless o therwise specified. 5 tested in parallel reading mode. 6 with all digital inputs forced to dvdd or dgnd respectively. specifications subject to change without notice. (?0 c to +85 c, avdd = dvdd = 5 v, ovdd = 2.7 v to 5.25 v, unless otherwise noted.) timing specifications symbol min typ max unit refer to figures 11 and 12 convert pulsewidth t 1 5ns time between conversions t 2 10 s cnvst low to busy high delay t 3 15 ns busy high all modes except in t 4 2 s master serial read after convert mode aperture delay t 5 2ns end of conversion to busy low delay t 6 10 ns conversion time t 7 2 s acquisition time t 8 8 s reset pulsewidth t 9 10 ns refer to figures 13, 14, and 15 (parallel interface modes) cnvst low to data valid delay t 10 2 s data valid to busy low delay t 11 45 ns bus access request to data valid t 12 40 ns bus relinquish time t 13 515ns refer to figure 16 and 17 (master serial interface modes) 1 cs low to sync valid delay t 14 10 ns cs low to internal sclk valid delay t 15 10 ns cs low to sdout delay t 16 10 ns cnvst low to sync delay t 17 0.5 s sync asserted to sclk first edge delay t 18 4ns internal sclk period t 19 40 75 ns internal sclk high (invsclk low) 2 t 20 30 ns internal sclk low (invsclk low) 2 t 21 9.5 ns sdout valid setup time t 22 4.5 ns sdout valid hold time t 23 3ns sclk last edge to sync delay t 24 3 cs high to sync hi-z t 25 10 ns cs high to internal sclk hi-z t 26 10 ns cs high to sdout hi-z t 27 10 ns busy high in master serial read after convert t 28 3.2 s cnvst low to sync asserted delay t 29 1.5 s sync deasserted to busy low delay t 30 50 ns refer to figures 18 and 20 (slave serial interface modes) 1 external sclk setup time t 31 5ns external sclk active edge to sdout delay t 32 316ns sdin setup time t 33 5ns sdin hold time t 34 5ns external sclk period t 35 25 ns external sclk high t 36 10 ns external sclk low t 37 10 ns notes 1 in serial interface modes, the sync, sclk, and sdout timings are defined with a maximum load c l of 10 pf; otherwise, the load is 60 pf maximum. 2 if the polarity of sclk is inverted, the timing references of sclk are also inverted. specifications subject to change without notice.
rev. c AD7660 C4C absolute maximum ratings 1 analog inputs in 2 , ref, ingnd, refgnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . avdd + 0.3 v to agnd C 0.3 v ground voltage differences agnd, dgnd, ognd . . . . . . . . . . . . . . . . . . . . . 0.3 v supply voltages avdd, dvdd, ovdd . . . . . . . . . . . . . . . . . . . . . . . . . 7 v avdd to dvdd, avdd to ovdd . . . . . . . . . . . . . 7 v dvdd to ovdd . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 v digital inputs except the data bus d(7:4) . . C0.3 v to dvdd + 0.3 v data bus inputs d(7:4) . . . . . C0.3 v to ovdd + 0.3 v internal power dissipation 3 . . . . . . . . . . . . . . . . . . . 700 mw junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . 150 c storage temperature range . . . . . . . . . . . . C65 c to +150 c lead temperature range (soldering 10 sec) . . . . . . . . . . . . . . . . . . . . . . . . . . 300 c notes 1 stresses above those listed under absolute maximum ratings may cause perma- nent damage to the device. this is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. 2 see analog input section. 3 specification is for device in free air: 48-lead lqfp: ja = 91 c/w, jc = 30 c/w. i oh 500 a 1.6ma i ol to output pin 1.4v c l 60pf 1 note 1 in serial interface modes, the sync, sclk, and sdout timings are defined with a maximum load c l of 10pf; otherwise, the load is 60pf maximum. figure 1. load circuit for digital interface timing caution esd (electrostatic discharge) sensitive device. electrostatic charges as high as 4000 v readily accumulate on the human body and test equipment and can discharge without detection. although the AD7660 features proprietary esd protection circuitry, permanent damage may occur on devices subjected to high-energy electrostatic discharges. therefore, proper esd precautions are recommended to avoid performance degradation or loss of functionality. warning! esd sensitive device ordering guide model temperature range package description package option AD7660ast C40 c to +85 c quad flatpack (lqfp) st-48 AD7660astrl C40 c to +85 c quad flatpack (lqfp) st-48 eval-AD7660cb 1 evaluation board eval-control brd2 2 controller board notes 1 this board can be used as a stand-alone evaluation board or in conjunction with the eval-control brd2 for evaluation/demonstration purposes. 2 this board allows a pc to control and communicate with all analog devices evaluation boards ending in the cb designators. pin configuration 48-lead lqfp (st-48) 36 35 34 33 32 31 30 29 28 27 26 25 13 14 15 16 17 18 19 20 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 48 47 46 45 44 39 38 37 43 42 41 40 pin 1 identifier top view (not to scale) agnd cnvst pd reset cs rd dgnd agnd avdd nc dgnd ob/ 2c nc nc ser/ par d0 d1 d2 busy d15 d14 d13 AD7660 d3 d12 d4/ext/ int d5/invsync d6/invsclk d7/rdc/sdin ognd ovdd dvdd dgnd d8/sdout d9/sclk d10/sync d11/rderror nc nc nc nc nc in nc nc nc ingnd refgnd ref nc = no connect t delay t delay 0.8v 0.8v 0.8v 2v 2v 2v figure 2. voltage reference levels for timings
rev. c AD7660 C5C pin function descriptions pin no. mnemonic type description 1 agnd p analog power ground pin 2 avdd p input analog power pins. nominally 5 v 3, 6, 7, nc no connect 40C42, 44C48 4 dgnd di must be tied to digital ground. 5ob/ 2c di straight binary/binary twos complement. when ob/ 2c is high, the digital output is straight binary; when low, the msb is inverted resulting in a twos complement output from its internal shift register. 8 ser/ par di serial/parallel selection input. when low, the parallel port is selected; when high, the serial interface mode is selected and some bits of the data bus are used as a serial port. 9C12 data[0:3] do bit 0 to bit 3 of the parallel port data output bus. these pins are always outputs regardless of the state of ser/ par . 13 data[4] di/o when ser/ par is low, this output is used as the bit 4 of the parallel port data output bus. or ext/ int when ser/ par is high, this input, part of the serial port, is used as a digital select input for choosing the internal or an external data clock. with ext/ int tied low, the internal clock is selected on sclk output. with ext/ int set to a logic high, output data is syn- chronized to an external clock signal connected to the sclk input. 14 data[5] di/o w hen ser/ par is low, this output is used as the bit 5 of the parallel port data output bus. or invsync when ser/ par is high, this input, part of the serial port, is used to select the active state of the sync signal. when low, sync is active high. when high, sync is active low. 15 data[6] di/o w hen ser/ par is low, this output is used as the bit 6 of the parallel port data output bus. or invsclk when ser/ par is high, this input, part of the serial port, is used to invert the sclk sig- nal. it is active in both master and slave mode. 16 data[7] di/o when ser/ par is low, this output is used as the bit 7 of the parallel port data output bus. or rdc/sdin when ser/ par is high, this input, part of the serial port, is used as either an external data input or a read mode selection input depending on the state of ext/ int . when ext/ int is high, rdc/sdin could be used as a data input to daisy chain the con- version results from two or more adcs onto a single sdout line. the digital data level on sdin is output on data with a delay of 16 sclk periods after the initiation of the read sequence. when ext/ int is low, rdc/sdin is used to select the read mode. when rdc/sdin is high, the data is output on sdout during conversion. when rdc/sdin is low, the data is output on sdout only when the conversion is complete. 17 ognd p input/output interface digital power ground 18 ovdd p input/output interface digital power. nominally at the same supply than the supply of the host interface (5 v or 3 v). 19 dvdd p digital power. nominally at 5 v. 20 dgnd p digital power ground 21 data[8] do when ser/ par is low, this output is used as the bit 8 of the parallel port data output bus. or sdout when ser/ par is high, this output, part of the serial port, is used as a serial data output synchronized to sclk. conversion results are stored in an on-chip register. the AD7660 provides the conversion result, msb first, from its internal shift register. the data format is determined by the logic level of ob/ 2c . in serial mode, when ext/ int is low, sdout is valid on both edges of sclk. in serial mode, when ext/ int is high: if invsclk is low, sdout is updated on sclk rising edge and valid on the next falling edge. if invsclk is high, sdout is updated on sclk falling edge and valid on the next rising edge.
rev. c AD7660 C6C pin function descriptions (continued) pin no. mnemonic type description 22 data[9] di/o when ser/ par is low, this output is used as the bit 9 of the parallel port data output bus. or sclk when ser/ par is high, this pin, part of the serial port, is used as a serial data clock input or output, dependent upon the logic state of the ext/ int pin. the active edge where the data sdout is updated depends upon the logic state of the invsclk pin. 23 data[10] do when ser/ par is low, this output is used as the bit 10 of the parallel port data output bus. or sync when ser /par is high, this output, part of the serial port, is used as a digital output frame synchronization for use with the internal data clock (ext/ int = logic low). when a read sequence is initiated and invsync is low, sync is driven high and remains high while sdout output is valid. when a read sequence is initiated and invsync is high, sync is driven low and remains low while sdout output is valid. 24 data[11] do when ser/ par is low, this output is used as the bit 11 of the parallel port data output bus. or rderror when ser/ par is high and ext/ int is high, this output, part of the serial port, is used as an incomplete read error flag. in slave mode, when a data read is started and not complete when the following conversion is complete, the current data is lost and rderror is pulsed high. 25C28 data[12:15] do bit 12 to bit 15 of the parallel port data output bus. these pins are always outputs regard- less of the state of ser/ par . 29 busy do busy output. transitions high when a conversion is started, and remains high until the conversion is complete and the data is latched into the on-chip shift register. the falling edge of busy could be used as a data ready clock signal. 30 dgnd p must be tied to digital ground. 31 rd di read data. when cs and rd are both low, the interface parallel or serial output bus is enabled. 32 cs di chip select. when cs and rd are both low, the interface parallel or serial output bus is enabled. cs is also used to gate the external clock. 33 reset di reset input. when set to a logic high, reset the AD7660. current conversion if any is aborted. 34 pd di power-down input. when set to a logic high, power consumption is reduced and conver- sions are inhibited after the current one is completed. 35 cnvst di start conversion. if cnvst is high when the acquisition phase (t 8 ) is complete, the next falling edge on cnvst puts the internal sample/hold into the hold state and initiates a con- version. this mode is the most appropriate if low sampling jitter is desired. if cnvst is low when the acquisition phase (t 8 ) is complete, the internal sample/hold is put into the hold state and a conversion is immediately started. 36 agnd p must be tied to analog ground. 37 ref ai reference input voltage 38 refgnd ai reference input analog ground 39 ingnd ai analog input ground 43 in ai primary analog input with a range of 0 v to v ref . notes ai = analog input di = digital input di/o = bidirectional digital do = digital output p = power
rev. c AD7660 C7C definition of specifications integral nonlinearity error (inl) linearity error refers to the deviation of each individual code from a line drawn from negative full scale through positive full scale. the point used as negative full scale occurs 1/2 lsb before the first code transition. positive full scale is defined as a level 1 1/2 lsb beyond the last code transition. the deviation is measured from the middle of each code to the true straight line. differential nonlinearity error (dnl) in an ideal adc, code transitions are 1 lsb apart. differential nonlinearity is the maximum deviation from this ideal value. it is often specified in terms of resolution for which no missing codes are guaranteed. full-scale error the last transition (from 011 . . . 10 to 011 . . . 11 in twos complement coding) should occur for an analog voltage 1 1/2 lsb below the nominal full scale (2.49994278 v for the 0 vC2.5 v range). the full-scale error is the deviation of the actual level of the last transition from the ideal level. unipolar zero error the first transition should occur at a level 1/2 lsb above analog ground (19.073 v for the 0 vC2.5 v range). unipolar zero error is the deviation of the actual transition from that point. spurious free dynamic range (sfdr) the difference, in decibels (db), between the rms amplitude of the input signal and the peak spurious signal. effective number of bits (enob) enob is a measurement of the resolution with a sine wave input. it is related to s/[n+d] by the following formula: enob = ( s /[ n + d ] db C 1.76)/6.02 and is expressed in bits. total harmonic distortion (thd) thd is the ratio of the rms sum of the first five harmonic components to the rms value of a full-scale input signal and is expressed in decibels. signal-to-noise ratio (snr) snr is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, excluding harmonics and dc. the value for snr is expressed in decibels. signal to (noise and distortion) ratio (s/[n+d]) s/(n+d) is the ratio of the rms value of the actual input signal to the rms sum of all other spectral components below the nyquist frequency, including harmonics but excluding dc. the value for s/(n+d) is expressed in decibels. aperture delay aperture delay is a measure of the acquisition performance, and is measured from the falling edge of the cnvst input to when the input signal is held for a conversion. transient response the time required for the AD7660 to achieve its rated accuracy after a full-scale step function is applied to its input.
rev. c AD7660 C8C typical performance characteristics code ? 0 inl ?lsb 16384 ? ? 0 1 2 3 32768 49152 65536 tpc 1. integral nonlinearity vs. code code 1.00 0 dnl lsb 16384 0.00 32768 49152 65536 0.75 0.50 1.00 1.75 1.50 1.25 0.75 0.25 0.50 0.25 tpc 4. differential nonlinearity vs. code frequency khz 0 10 20304050 amplitude db of full scale 180 120 40 0 80 140 60 20 100 160 4096 point fft f s = 100khz f in = 45khz snr = 90.14db sinad = 89.94db thd = 101.37db sfdr = 110db tpc 7. fft plot positive inl lsb 0 0 number of units 0.6 5 10 15 20 25 30 1.2 1.8 2.4 3.0 tpc 2. typical positive inl distribution (350 units) negative inl lsb 0 0 number of units 0.6 5 10 15 20 25 30 1.2 1.8 2.4 3.0 35 tpc 5. typical negative inl distribution (350 units) 130 1 thd, harmonics db 10 100 1000 90 80 60 70 100 120 110 sfdr thd 60 sfdr db 90 100 120 110 80 70 2 nd harmonic 3 rd harmonic frequency khz tpc 8. thd, harmonics, and sfdr vs. frequency code hexa 0 counts 8008 8000 7000 6000 5000 4000 3000 2000 1000 0 8009 800a 800b 800c 800d 800e 800f 8010 8011 013 9 0 0 879 1213 7051 7219 tpc 3. histogram of 16,384 conversions of a dc input at the code transition code hexa 0 counts 10000 8000 6000 4000 0 8009 800a 800b 800c 800d 800e 800f 8010 8011 0 188 00 161 2000 9026 3520 3489 tpc 6. histogram of 16,384 conversions of a dc input at the code center input level db 140 90 thd, harmonics db 90 80 60 70 100 120 110 thd 2 nd harmonic 3 rd harmonic 80 0 10 20 30 40 50 60 70 130 tpc 9. thd, harmonics vs. input level
rev. c AD7660 C9C frequency hz 1 snr and s/(n+d) db 10 100 1k snr s/(n+d) 13.0 enob bits 14.5 15.0 16.0 15.5 14.0 13.5 70 85 90 100 95 80 75 enob tpc 10. snr, s/(n+d), and enob vs. frequency sampling rate sps 10m 0.1 operating currents na 1m 100k 10k 1k 100 10 1 1 10 100 1k 10k 100k 1m av d d dvdd ovdd tpc 13. operating currents vs. sample rate temperature c 10 40 power-down operating currents na 10 60 110 50 60 100 80 20 0 10 15 35 85 30 40 70 90 dvdd av d d ovdd tpc 14. power-down operating currents vs. temperature input level db 50 snr (referred to full scale) db 40 20 0 86 90 92 88 30 10 tpc 11. snr vs. input level (referred to full scale) c l pf 0 t 12 delay ns 50 100 200 0 20 30 50 40 10 150 ovdd @ 2.7v, 85 c ovdd @ 2.7v, 25 c ovdd @ 5v, 85 c ovdd @ 5v, 25 c tpc 12. typical delay vs. load capacitance c l
rev. c AD7660 C10C circuit information the AD7660 is a fast, low-power, single-supply, precise 16-bit analog-to-digital converter (adc). the AD7660 is capable of converting 100,000 samples per second (100 ksps) and allows power saving between conversions. when operating at 100 sps, for example, it consumes typically only 21 w. this feature makes the AD7660 ideal for battery-powered applications. the AD7660 provides the user with an on-chip track/hold, successive approximation adc that does not exhibit any pipe- line or latency, making it ideal for multiple multiplexed channel applications. the AD7660 can be operated from a single 5 v supply and be interfaced to either 5 v or 3 v digital logic. it is ho used in a 48-lead lqfp package that combines space savings and allows flexible configurations as either serial or parallel interface. the AD7660 is pin-to-pin-compatible with the ad7664. converter operation the AD7660 is a successive approximation analog-to-digital converter based on a charge redistribution dac. figure 3 shows the simplified schematic of the adc. the capacitive dac consists of an array of 16 binary weighted capacitors and an additional lsb capacitor. the comparators negative input is connected to a dummy capacitor of the same value as the capacitive dac array. during the acquisition phase, the common terminal of the array tied to the comparators positive input is connected to agnd via sw a . all independent switches are connected to the analog input in. thus, the capacitor array is used as a sampling capaci- tor and acquires the analog signal on in input. similarly, the dummy capacitor acquires the analog signal on ingnd input. when the acquisition phase is complete and the cnvst input goes or is low, a conversion phase is initiated. when the conver- sion phase begins, sw a and sw b are opened first. the capacitor array and the dummy capacitor are then disconnected from the inputs and connected to the refgnd input. therefore, the differential voltage between in and ingnd captured at the end of the acquisition phase is applied to the comparator inputs, caus- ing the comparator to become unbalanced. by switch ing each element of the ca pacitor array between r efgnd or ref, the comparator input varies by binary weighted voltage steps (v ref /2, v ref /4...v ref /65536). the control logic toggles these switches, starting with the msb first, in order to bring the comparator back into a balanced condition. after the comple- tion of this process, the control logic generates the adc output code and brings busy output low. sw a comp sw b in ref refgnd lsb lsb msb 32768c ingnd 16384c 4c 2c c 67536c control logic switches control busy output code cnvst c figure 3. adc simplified schematic
rev. c AD7660 C11C 100nf 10 f 100nf 10 f avdd 10 f 100nf agnd dgnd dvdd ovdd ognd cs rd ser/ par cnvst busy sdout sclk reset pd in ingnd note 2 u1 refgnd c ref note 1 2.5v ref note 1 ref 100 d note 3 clock AD7660 analog input (0v to 2.5v) c/ p/dsp serial port digital supply (3.3v or 5v) analog supply (5v) dvdd ob/ 2c notes 1. with the ad780 or the adr291 voltage reference, c ref is 47 f, see voltage reference input section. 2. the ad8519 is recommended. 3. optional low jitter cnvst. figure 5. typical connection diagram transfer functions using the ob/ 2c digital input, the AD7660 offers two output codings: straight binary and twos complement. the lsb size is v ref /65536, which is about 38.15 v. the ideal transfer charac- teristic for the AD7660 is shown in figure 4 and table i. 000...000 000...001 000...010 111...101 111...110 111...111 adc code straight binary analog input v ref 1.5 lsb v ref 1 lsb 1 lsb 0v 0.5 lsb 1 lsb = v ref /65536 figure 4. adc ideal transfer function table i. output codes and ideal input voltages digital output code (hexa) analog straight two? description input binary complement fsr C 1 lsb 2.499962 v ffff 1 7fff 1 fsr C 2 lsb 2.499923 v fffe 7ffe midscale + 1 lsb 1.250038 v 8001 0001 midscale 1.25 v 8000 0000 midscale C 1 lsb 1.249962 v 7fff ffff Cfsr + 1 lsb 38 v 0001 8001 Cfsr 0 v 0000 2 8000 2 notes 1 this is also the code for overrange analog input (v in C v ingnd above v ref C v refgnd ). 2 this is also the code for underrange analog input (v in below v ingnd ). typical connection diagram figure 5 shows a typical connection diagram for the AD7660.
rev. c AD7660 C12C analog input figure 6 shows an equivalent circuit of the input structure of the AD7660. c2 r1 d1 d2 c1 in or ingnd agnd avdd figure 6. equivalent analog input circuit the two diodes d1 and d2 provide esd protection for the analog inputs in and ingnd. care must be taken to ensure that the analog input signal never exceeds the supply rails by more than 0.3 v. this will cause these diodes to become for- ward-biased and start conducting current. these diodes can handle a forward-biased current of 100 ma maximum. for instance, these conditions could eventually occur when the input buffers (u1) supplies are different from avdd. in such case, an input buffer with a short circuit current limitation can be used to protect the part. this analog input structure allows the sampling of the differen- tial signal between in and ingnd. unlike other converters, the ingnd input is sampled at the same time as the in input. by using this differential input, small signals common to both inputs are rejected as shown in figure 7 which represents the typical cmr over frequency. for instance, by using ingnd to sense a remote signal ground, difference of ground potentials between the sensor and the local adc ground are eliminated. frequency hz cmrr db 45 75 10k 10m 1k 1m 80 65 100k 55 85 70 60 50 40 figure 7. analog input cmr vs. frequency during the acquisition phase, the impedance of the analog input in can be modeled as a parallel combination of capacitor c1 and the network formed by the series connection of r1 and c2. capacitor c1 is primarily the pin capacitance. the resistor r1 is typically 3242 ? and is a lumped component made up of some serial resistor and the on resistance of the switches. the capacitor c2 is typically 60 pf and is mainly the adc sampling capacitor. during the conversion phase, where the switches are opened, the input impedance is limited to c1. it has to be noted that the input impedance of the AD7660, unlike other sar adcs, is not a pure capacitance and thus, inherently reduces the kickback transient at the beginning of the acquisition phase. the r1, c2 makes a one- pole low-pass filter with a typical cutoff frequency of 820 khz, that reduces undesirable aliasing effect and limits the noise. when the source impedance of the driving circuit is low, the AD7660 can be driven directly. large source impedances will significantly affect the ac performances, especially the total harmonic distortion. the maximum source impedance depends on the amount of total harmonic distortion (thd) that can be tolerated. the thd degrades in function of the source imped- ance and the maximum input frequency as shown in figure 8. input frequency khz 100 1 100 10 thd db 95 90 85 80 75 70 r s = 500 r s = 100 r s = 50 r s = 20 figure 8. thd vs. analog input frequency and input resistance driver amplifier choice although the AD7660 is easy to drive, the driver amplifier needs to meet at least the following requirements: ? the driver amplifier and the AD7660 analog input circuit have to be able together to settle for a full-scale step the capacitor array at a 16-bit level (0.0015%). for instance, operation at the maximum throughput of 100 ksps requires a minimum gain bandwidth product of 5 mhz. ? the noise generated by the driver amplifier needs to be kept as low as possible in order to preserve the snr and transi- tion noise performance of the AD7660. the noise coming from the driver is filtered by the AD7660 analog input circuit one-pole low-pass filter made by r1 and c2. for instance, a driver with an equivalent input noise of 7 nv/ hz like the ad8519 and configured as a buffer, thus with a noise gain of +1, degrades the snr by only 0.2 db. ? the driver needs to have a thd performance suitable to that of the AD7660. tpc 8 gives the thd versus frequency that the driver should preferably exceed. the snr degradation due to the amplifier is : snr fne loss db n = + ? ? ? ? ? ? ? ? ? ? ? ? 20 28 784 4 3 2 log C () where f ?db is the C3 db input bandwidth of the AD7660 (0.82 mhz) or the cutoff frequency of the input filter if any are used. n is the noise factor of the amplifier (1 if in buffer configuration) e n is the equivalent input noise voltage of the op-amp in nv/(hz) 1/2 .
rev. c AD7660 C13C the ad8519, op162, or the op184 meet these requirements and are usually appropriate for almost all applications. as an alternative, in very high-speed and noise-sensitive applications, the ad8021 with an external compensation capacitor of 10 pf, or the ad829 with an external compensation capacitor of 82 pf, can be used. this capacitor should have good linearity as an npo ceramic or mica type. moreover, the use of a noninverting +1 gain arrangement is recommended and helps to obtain the best signal-to-noise ratio. voltage reference input the AD7660 uses an external 2.5 v voltage reference. the voltage reference input ref of the AD7660 has a dynamic input impedance; it should therefore be driven by a low- impedance source with an efficient decoupling between ref and refgnd inputs. this decoupling depends on the choice of the voltage reference but usually consists of a 1 f ceramic capacitor and a low esr tantalum capacitor connected to the ref and refgnd inputs with minimum parasitic inductance. 47 f is an appropriate value for the tantalum capacitor when used with one of the recommended reference voltages: ? the low noise, low temperature drift adr421 and ad780 voltage references ? the low power adr291 voltage reference ? the low cost ad1582 voltage reference for applications using multiple AD7660s, it is more effective to buffer the reference voltage with a low-noise, very stable op amp like the ad8031. care should also be taken with the reference temperature coeffi- cient of the voltage reference which directly affects the full-scale accuracy if this parameter matters. for instance, a 15 ppm/ c tempco of the reference changes the full scale by 1 lsb/ c. v ref , as mentioned in the specification table, could be in creased to avdd C 1.85 v. the benefit here is the increased snr obtained as a result of this increase. since the input range is defined in terms of v ref , this would essentially increase the range to make it a 3 v input range with an avdd above 4.85 v. one of the benefits here is the increase snr obtained as a result of this increase. the theoretical improvement as a result of this increase in reference is 1.58 db (20 log [3/2.5]). due to the theoretical quantization noise, however, the observed improvement is approximately 1 db. the ad780 can be selected with a 3 v reference voltage. power supply the AD7660 uses three sets of power supply pins: an analog 5 v supply avdd, a digital 5 v core supply dvdd, and a digital input/output interface supply ovdd. the ovdd supply allows direct interface with any logic working between 2.7 v and 5.25 v. to reduce the number of supplies needed, the digital core (dvdd) can be supplied through a simple rc filter from the analog supply as shown in figure 5. the AD7660 is independent of power supply sequencing and thus free from supply voltage induced latchup. additionally, it is very insensitive to power supply variations over a wide frequency range as shown in figure 9. input frequency hz psrr db 80 1k 10k 100k 1m 75 70 65 60 55 50 figure 9. psrr vs. frequency power dissipation vs. throughput the AD7660 automatically reduces its power consumption at the end of each conversion phase. during the acquisition phase, the operating currents are very low which allows a significant power saving when the conversion rate is reduced as shown in figure 10. this feature makes the AD7660 ideal for very low- power battery applications. it should be noted that the digital interface remains active even during the acquisition phase. to reduce the operating digital supply currents even further, the digital inputs need to be driven close to the power rails (i.e., dvdd and dgnd for all inputs except ext/ int , invsync, invsclk, rdc/sdin, and ovdd or ognd for the last four inputs. throughput sps 100 10 power dissipation mw 1 100 0.01 10 1000 10000 100000 0.1 figure 10. power dissipation vs. sample rate
rev. c AD7660 C14C conversion control figure 11 shows the detailed timing diagrams of the conversion process. the AD7660 is controlled by the signal cnvst which initiates conversion. once initiated, it cannot be restarted or aborted, even by the power-down input pd, until the conver- sion is complete. the cnvst signal operates independently of cs and rd signals. cnvst busy mode t 2 t 1 t 3 t 4 t 5 t 6 t 7 t 8 acquire convert acquire convert figure 11. basic conversion timing for a true sampling application, the recommended operation of the cnvst signal is the following: cnvst must be held high from the previous falling edge of busy, and during a minimum delay corresponding to the acquisition time t8; then, when cnvst is brought low, a con- version is initiated and busy signal goes high until the completion of the conversion. although cnvst is a digital signal, it should be designed with special care with fast, clean edges and levels, with minimum overshoot and undershoot or ringing. for appli- cations where the snr is critical, the cnvst signal should have a very low jitter. some solutions to achieve this are to use a dedicated oscillator for cnvst generation or, at least, to clock it with a high frequency low jitter clock as shown in figure 5. t 9 t 8 reset data busy cnvst figure 12. reset timing for other applications, conversions can be automatically initi- ated. if cnvst is held low when busy is low, the AD7660 controls the acquisition phase and then automatically initiates a new conversion. by keeping cnvst low, the AD7660 keeps the conversion process running by itself. it should be noted that the analog input has to be settled when busy goes low. also, at power-up, cnvst should be brought low once to initiate the conversion process. in this mode, the AD7660 could sometimes run slightly faster than the guaranteed limit of 100 ksps. digital interface the AD7660 has a versatile digital interface; it can be interfaced with the host system by using either a serial or parallel interface. the serial interface is multiplexed on the parallel data bus. the AD7660 digital interface also accommodates both 3 v or 5 v logic by simply connecting the ovdd supply pin of the AD7660 to the host system interface digital supply. finally, by using the ob/ 2c input pin, both twos complement or straight binary coding can be used. the two signals cs and rd control the interface. when at least one of these signals is high, the interface outputs are in high impedance. usually, cs allows the selection of each AD7660 in multicircuits applications and is held low in a single AD7660 design. rd is generally used to enable the conversion result on the data bus. t 1 t 3 t 4 t 11 cnvst busy data bus cs = rd = 0 t 10 previous conversion data new data figure 13. master parallel data timing for reading (continuous read) parallel interface the AD7660 is configured to use the parallel interface when the ser/ par is held low. the data can be read either after each conversion, which is during the next acquisition phase, or during the following conversion as shown, respectively, in figure 14 and figure 15. when the data is read during the conversion, how- ever, it is recommended, that it is read only during the first half of the con version phase. that avoids any potential feedthrough between voltage transients on the digital interface and the most critical analog conversion circuitry. current conversion busy data bus cs rd t 12 t 13 figure 14. slave parallel data timing for reading (read after convert)
rev. c AD7660 C15C previous conversion t 1 t 3 t 12 t 13 t 4 cs = 0 cnvst , rd busy data bus figure 15. slave parallel data timing for reading (read during convert) serial interface the AD7660 is configured to use the serial interface when the ser/ par is held high. the AD7660 outputs 16 bits of data, msb first, on the sdout pin. this data is synchronized with the 16 clock pulses provided on the sclk pin. master serial interface internal clock the AD7660 is configured to generate and provide the serial data clock sclk when the ext/ int pin is held low. the AD7660 also generates a sync signal to indicate to the host when the serial data is valid. the serial clock sclk and the sync signal can be inverted if desired. the output data is valid on both the rising and falling edge of the data clock. depending on rdc/ sdin input, the data can be read after each conversion, or during the following conversion. figure 16 and figure 17 show the detailed timing diagrams of these two modes. usually, because the AD7660 has a longer acquisition phase than the conversion phase, the data is read immediately after conversion. that makes the mode master, read after conversion, the most recommended serial mode when it can be used. in read-after-conversion mode, it should be noted that, unlike in other modes, the signal busy returns low after the 16 data bits are pulsed out and not at the end of the conversion phase which results in a longer busy width. in read-during-conversion mode, the serial clock and d ata toggle at appropriate instants, which minimizes potential feedthrough between digital activity and the critical conversion decisions. t 3 busy cs , rd cnvst sync sclk sdout t 28 t 29 t 14 t 18 t 19 t 20 t 21 t 24 t 26 t 27 t 23 t 22 t 16 t 15 123 141516 d15 d14 d2 d1 d0 x ext/ int = 0 rdc/sdin = 0 invsclk = invsync = 0 t 25 t 30 figure 16. master serial data timing for reading (read after convert)
rev. c AD7660 C16C slave serial interface external clock the AD7660 is configured to accept an externally supplied serial data clock on the sclk pin when the ext/ int pin is held high. in this mode, several methods can be used to read the data. when cs and rd are both low, the data can be read after each conversion or during the following conversion. the exter- nal clock can be either a continuous or discontinuous clock. a discontinuous clock can be either normally high or normally low when inactive. figure 18 and figure 20 show the detailed timing diagrams of these methods. usually, because the AD7660 has a longer acquisition phase than the conversion phase, the data are read immediately after conversion. while the AD7660 is performing a bit decision, it is important that voltage transients not occur on digital input/output pins or degradation of the conversion result could occur. this is par- ticularly important during the second half of the conversion ext/ int = 0 rdc/sdin = 1 invsclk = invsync = 0 t 3 t 1 t 17 t 14 t 19 t 20 t 21 t 24 t 26 t 25 t 27 t 23 t 22 t 16 t 15 d15 d14 d2 d1 d0 x 12 3 141516 t 18 busy cs , rd cnvst sync sclk sdout figure 17. master serial data timing for reading (read previous conversion during convert) phase because the AD7660 provides error correction circuitry that can correct for an improper bit decision made during the first half of the conversion phase. for this reason, it is recom- mended that when an external clock is being provided, it is a discontinuous clock that is toggling only when busy is low or, more importantly, that it does not transition during the latter half of busy high. external discontinuous clock data read after conversion this mode is the most recommended of the serial slave modes. figure 18 shows the detailed timing diagrams of this method. after a conversion is complete, indicated by busy returning low, the result of this conversion can be read while both cs and rd are low. the data is shifted out, msb first, with 16 clock pulses and is valid on both rising and falling edge of the clock. among the advantages of this method, the conversion perfor- mance is not degraded because there is no voltage transients on the digital interface during the conversion process. sclk sdout d15 d14 d1 d0 d13 x15 x14 x13 x1 x0 y15 y14 cs busy sdin ext/ int = 1 invsclk = 0 t 35 t 36 t 37 t 31 t 32 t 16 t 33 x15 x14 x 1 2 3 14151617 18 rd = 0 t 34 figure 18. slave serial data timing for reading (read after convert)
rev. c AD7660 C17C another advantage is to be able to read the data at any speed up to 40 mhz which accommodates both slow digital host interface and the fastest serial reading. finally, in this mode only, the AD7660 provides a daisy chain feature using the rdc/sdin input pin for cascading multiple converters together. this feature is useful for reducing compo- nent count and wiring connections when it is desired as it is, for instance, in isolated multiconverters applications. an example of the concatenation of two devices is shown in figure 19. simultaneous sampling is possible by using a common cnvst signal. it should be noted that the rdc/sdin input is latched on the opposite edge of sclk of the one used to shift out the data on sdout. hence, the msb of the upstream converter just follows the lsb of the downstream converter on the next sclk cycle. up to twenty AD7660s running at 100 ksps can be daisy chained using this method. sclk sdout rdc/sdin busy busy data out AD7660 #1 (downstream) busy out cnvst cs sclk AD7660 #2 (upstream) rdc/sdin sdout sclk in cs in cnvst in cnvst cs figure 19. two AD7660s in a daisy chain configuration external clock data read during conversion figure 20 shows the detailed timing diagrams of this me thod. during a conversion, while both cs and rd are low, the result of the previous conversion can be read. the data is shifted out, msb first, with 16 clock pulses, and is valid on both rising and falling edges of the clock. the 16 bits have to be read before the current conversion is complete. if that is not done, rderror is pulsed high and can be used to interrupt the host interface to prevent incomplete data reading. there is no daisy chain feature in this mode, and rdc/sdin input should always be tied either high or low. to reduce performance degradation due to digital activity, a fast discontinuous clock of 18 mhz at least is recommended to ensure that all the bits are read during the first half of the conversion phase. for this reason, this mode is more difficult to use. microprocessor interfacing the AD7660 is ideally suited for traditional dc measurement applications supporting a microprocessor, and ac signal process- ing applications interfacing to a digital signal processor. the AD7660 is designed to interface either with a parallel 16-bit- wide interface or with a general purpose serial port or i/o ports on a microcontroller. a variety of external buffers can be used with the AD7660 to prevent digital noise from coupling into the adc. the following sections illustrate the use of the AD7660 with an spi equipped microcontroller, the adsp-21065l and adsp-218x signal processors. sdout cs sclk d1 d0 x d15 d14 d13 123 141516 t 3 t 35 t 36 t 37 t 31 t 32 t 16 cnvst busy ext/ int = 1 invsclk = 0 rd = 0 figure 20. slave serial data timing for reading (read previous conversion during convert)
rev. c AD7660 C18C spi interface (mc68hc11) figure 21 shows an interface diagram between the AD7660 and an spi-equipped microcontroller like the mc68hc11. to accommodate the slower speed of the microcontroller, the AD7660 acts as a slave device and data must be read after conversion. this mode also allows the daisy chain feature. the convert command could be initiated in response to an internal timer interrupt. the reading of output data, one byte at a time, if necessary, could be initiated in response to the end-of-conversion signal (busy going low) using an interrupt line of the microcontroller. the serial peripheral interface (spi) on the mc68hc11 is configured for master mode (mstr) = 1, clock polarity bit (cpol) = 0, clock phase bit (cpha) = 1 and spi interrupt enable (spie) = 1 by writing to the spi control register (spcr). the irq is configured for edge-sensitive-only operation (irqe = 1 in option register). irq mc68hc11 * cnvst AD7660 * busy cs miso/sdi sck i/o port sdout sclk invsclk ext/ int dvdd * additional pins omitted for clarity ovdd ser/ par rd figure 21. interfacing the AD7660 to spi interface adsp-21065l in master serial interface as shown in figure 22, the AD7660 can be interfaced to the adsp-21065l using the serial interface in master mode with- out any glue logic required. this mode combines the advan- tages to reduce the wire connections and to be able to read the data during or after conversion at user convenience. rfs adsp-21065l * sharc cnvst AD7660 * cs sync rd dr rclk flag or tfs sdout sclk invsync invsclk ext/ int rdc/sdin ser/ par dvdd * additional pins omitted for clarity ovdd or ognd figure 22. interfacing to the adsp-21065l using the serial master mode the AD7660 is configured for the internal clock mode (ext/ int low) and acts, therefore, as the master device. the convert com- mand can be generated by either an external low jitter oscillator or, as shown, by a flag output of the adsp-21065l or by a frame output tfs of one serial port of the adsp-21065l which can be used like a timer. the serial port on the adsp-21065l is configured for external clock (irfs = 0), rising edge active (ckre = 1), external late framed sync signals (irfs = 0, lafs = 1, rfsr = 1) and active high (lrfs = 0). the serial port of the adsp-21065l is configured by writing to its receive control register (srctl)see adsp-2106x sharc u sers manual. because the serial port, within the adsp-21065l will be seeing a discontinuous clock, an initial word reading has to be done after the adsp-21065l has been reset to ensure that the serial port is properly synchronized to this clock during each following data read operation. application hints bipolar and wider input ranges in some applications, it is desired to use a bipolar or wider analog input range like, for instance, 10 v, 5 v, or 0 v to 5 v. although the AD7660 has only one unipolar range, by simple modifications of the input driver circuitry, bipolar and wider input ranges can be used without any performance degradation. figure 23 shows a connection diagram which allows that. compo- nent values required and resulting full-scale ranges are shown in table ii. u1 2.5v ref analog input r2 r3 r4 100nf r1 c f u2 c ref in ingnd ref refgnd 100nf AD7660 figure 23. using the AD7660 in 16-bit bipolar and/or wider input ranges table ii. component values and input ranges input range r1 r2 r3 r4 10 v 1 k ? 8 k ? 10 k ? 8 k ? 5 v 2 k ? 8 k ? 10 k ? 6.67 k ? 0 v to C5 v 8 k ? 8 k ? none 0 ? for bipolar range applications where accurate gain and offset are desired, they can be calibrated by acquiring a ground and a voltage reference using an analog multiplexer u2 as shown in figure 23. also, c f can be used as a one-pole antialiasing filter.
rev. c AD7660 C19C layout the AD7660 has very good immunity to noise on the power supplies as can be seen in figure 9. however, care should still be taken with regard to grounding layout. the printed circuit board that houses the AD7660 should be designed so the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be easily separated. digital and analog ground planes should be joined in only one place, preferably underneath the AD7660, or, at least, as close as possible to the AD7660. if the AD7660 is in a system where multiple devices require analog to digital ground connections, the connection should still be made at one point only, a star ground point, which should be established as close as possible to the AD7660. it is recommended to avoid running digital lines under the device as these will couple noise onto the die. the analog ground plane should be allowed to run under the AD7660 to avoid noise coupling. fast switching signals like cnvst or clocks should be shielded with digital ground to avoid radiating noise to other sections of the board, and should never run near analog signal paths. crossover of digital and analog signals should be avoided. traces on different but close layers of the board should run at right angles to each other. this will reduce the effect of feedthrough through the board. the power supply lines to the AD7660 should use as large a trace as possible to provide low impedance paths and reduce the effect of glitches on the power supply lines. good decoupling is also important to lower the supplies impedance presented to the AD7660 and reduce the magnitude of the supply spikes. decoupling ceramic capacitors, typically 100 nf, should be placed on each power supplies pins avdd, dvdd and ovdd close to, and ideally right up against these pins and their corre- sponding ground pins. additionally, low esr 10 f capacitors should be located in the vicinity of the adc to further reduce low frequency ripple. the dvdd supply of the AD7660 can be either a separate supply or come from the analog supply, avdd, or from the digital interface supply, ovdd. when the system digital supply is noisy, or fast switching digital signals are present, it is recom- mended if no separate supply available, to connect the dvdd digital supply to the analog supply avdd through an rc filter as shown in figure 6, and connect the system supply to the inter- face digital supply ovdd and the remaining digital circuitry. when dvdd is powered from the system supply, it is useful to insert a bead to further reduce high-frequency spikes. the AD7660 has five different ground pins; ingnd, refgnd, agnd, dgnd, and ognd. ingnd is used to sense the analog input signal. refgnd senses the reference voltage and should be a low impedance return to the reference because it carries pulsed currents. agnd is the ground to which most internal adc analog signals are referenced. this ground must be con- nected with the least resistance to the analog ground plane. dgnd must be tied to the analog or digital ground plane depend- ing on the configuration. ognd is connected to the digital system ground. evaluating the AD7660 performance a recommended layout for the AD7660 is outlined in the evalu- ation board for the AD7660. the evaluation board package includes a fully assembled and tested evaluation board, docu- mentation, and software for controlling the board from a pc via the eval-control board.
rev. c C20C AD7660 outline dimensions dimensions shown in inches and (mm). c01928C0C1/02(c) printed in u.s.a. 48-lead quad flatpack (lqfp) (st-48) controlling dimensions are in millimeters; inch dimensions are rounded-off millimeter equivalents for reference only and are not appropriate for use in design top view (pins down) 1 12 13 25 24 36 37 48 0.019 (0.5) bsc 0.276 (7.00) bsc sq 0.011 (0.27) 0.006 (0.17) 0.354 (9.00) bsc sq 0.063 (1.60) max 0.030 (0.75) 0.018 (0.45) 0.008 (0.20) 0.004 (0.09) 0 min coplanarity 0.003 (0.08) seating plane 0.006 (0.15) 0.002 (0.05) 7 0 0.057 (1.45) 0.053 (1.35) revision history location page 01/02?ata sheet changed from rev. b to rev. c. edits to features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edits to functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 edits to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 edits to pin function discription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 edits to driver amplifier choice section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 new voltage reference input section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 edits to digital interface section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 new st-48 package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 09/01?ata sheet changed from rev. a to rev. b. edit to specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 edit to timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 edit to absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 edit to ordering guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 edit to typical performance characteristics graphs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9, 10 edit to driver amplifier choice section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 edit to figure 18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 edit to figure 20 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 edit to table ii . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 edit to bipolar and wider input ranges section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19

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